1. Field of the Invention
The present invention relates to a semiconductor device having a contact of SiGe combined with cobalt silicide at a metal/semiconductor interface, and more particularly to a process for fabricating low resistance contact for DRAM by a hybrid contact method.
2. Description of the Prior Art
It has been customary in modern semiconductor manufacturing technique to form MS (metal-semiconductor) contact by forming is either an Ohmic contact or a diffusion contact. The former technique is performed by implantation dopants into the MS interface layer to a concentration above solid solubility limit (i.e. N(n,p) greater than 1020 cmxe2x88x923) to form a tunneling barrier. On the other hand, the latter technique is performed by diffusing dopants into the interface layer to lower the Schottky Barrier Height (SBH).
Silicon, a frequently used semiconductor, has a high intrinsic SBH (or Eg (energy gap)), Eg=1.11 eV. Therefore, when silicon is used, a relatively high doping concentration is required at the MS interface layer, which is usually performed using high-energy implantation, to lower the SBH in order to form a better contact. However, the high-energy implantation results in unwanted deep contact junctions, which subjects the device to short channel effect (SCE) or punch-through (leakage).
An object of the present invention is to solve the above-mentioned problems and provide a semiconductor device having a metal/semiconductor interface with low resistance contact and low cost.
Another object of the present invention is to provide a process to form a low resistance contact at a metal/semiconductor interface using moderate doping requirements, which in turn protects the device from short channel effect and leakage.
A further object of the present invention is to provide a process to form a metal contact for a memory device such as dynamic random access memory (DRAM) by a hybrid contact method, which can reduce mask steps and in turn cut down the production costs.
To achieve the above objects, according to a first aspect of the present invention, the semiconductor device of the present invention includes a semiconductor substrate; a dielectric layer on the semiconductor substrate, having a contact opening exposing the semiconductor substrate; a SixGe1xe2x88x92x layer formed within the contact opening on the semiconductor substrate, wherein 0 less than x less than 1; a cobalt silicide layer on the SixGe1xe2x88x92x layer; a conformal cobalt layer both on the cobalt silicide layer and on the sides of the contact opening; and a metal plug over the cobalt layer filling the contact opening.
According to a second aspect of the present invention, the process to form a metal contact for a memory device includes providing a semiconductor substrate having a first FET of a first conductivity type and a second FET of a second conductivity type in a support area and a third FET of the second conductivity type in an array area; providing a first diffusion region adjacent to the first FET, a second diffusion region adjacent to the second FET, and a third diffusion region adjacent to the third FET; forming a dielectric layer on the semiconductor substrate; respectively forming first, second, and third contact openings in the dielectric layer to the first, second, third diffusion regions; forming a doped SixGe1xe2x88x92x layer of a second conductivity type within the first, second, and third contact openings, wherein 0 less than x less than 1; masking the second and third contact openings; removing the doped SixGe1xe2x88x92x layer within the first contact opening; implantation a dopant of a first conductivity type into the first diffusion region; conformally forming a cobalt layer over the semiconductor substrate; transforming the cobalt layer into a cobalt silicide layer by reacting the cobalt layer with the underlying SixGe1xe2x88x92x layer in the second and third contacting openings; diffusing the dopant in the doped SixGe1xe2x88x92x layer within the second and third contact openings into the second and third diffusion regions; and filling a metal plug into the first, second, and third contact openings.
According to a third aspect of the present invention, the process to form a metal contact for a dynamic random access memory (DRAM) includes providing a semiconductor substrate having a pFET and an nFET in a support area and an nFET in an array area; providing a first source/drain region adjacent to the pFET in the support area, a second source/drain region adjacent to the nFET in the support area, and a third source/drain region adjacent to the nFET in the array area; forming a dielectric layer on the semiconductor substrate; respectively forming first, second, and third contact openings in the dielectric layer to the first, second, third source/drain regions; forming an n-doped SixGe1xe2x88x92x layer within the first, second, and third contact openings, wherein 0 less than x less than 1; masking the second and third contact openings; removing the n-doped SixGe1xe2x88x92x layer within the first contact opening; implantation a p-type dopant into the first source/drain region; conformally forming a cobalt layer over the semiconductor substrate; transforming the cobalt layer into a cobalt silicide layer by reacting the cobalt layer with the underlying SixGe1xe2x88x92x layer in the second and third contacting openings; diffusing the n-type dopant in the n-doped SixGe1xe2x88x92x layer within the second and third contact openings into the second and third source/drain regions; and filling a metal plug into the first, second, and third contact openings.